The power module topology is half bridge. The main intention for creating such dual power module is reducing the module’s internal stray inductance. In order to minimize the internal voltage spike – one of the bottlenecks for keeping the RBSOA at maximum inverter output current. Each new chip generation shows increased current switching slope di/dt causing higher overvoltage spikes inside the package if the power module’s stray inductance would be kept constant. The issue becomes even more...
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