Testing integrated circuits

The main advantage of analyzing a device’s immunity at the integrated circuit level is that such testing does not require consideration of the influence of the circuit’s design on electromagnetic compatibility (EMC). This analysis includes, for example, the design of the printed circuit board, the nature and availability of connectors, and the enclosure. The article describes the relationship between testing at the device level and at the integrated circuit (IC) level.

Introduction

Ensuring compliance with EMC standards is becoming an increasingly demanding issue. Technological progress has allowed for the reduction of component sizes, but it has also created a particular challenge: controlling the device's immunity to electromagnetic interference.

Current immunity requirements significantly increase the cost of designing and manufacturing devices. However, by testing immunity at the component level (i.e., integrated circuits), issues can be more easily identified and corrective actions taken. The results of immunity tests allow for preliminary selection of specific integrated circuits (including ASICs) for further product development. Additionally, they can be incorporated into IC analysis and contribute to component optimization.

Although there are already testing procedures in the industry that have allowed for the accumulation of substantial experience in assessing IC immunity, the concept behind the current testing method introduces a certain change. It involves applying disturbance pulses directly to the pins of the tested ICs. The shape and amplitude of the disturbances are specifically selected to mimic typical phenomena that the IC would be exposed to during a standard immunity test of a device containing that circuit or during operation in a disturbed environment.

During operation, technical equipment, objects, and devices are usually powered by pulsing interference signals. Therefore, standard device tests simulate, for example, spark generation at a switch contact (burst) or electrostatic discharge (ESD).

In the case of the standard testing method, immunity is observed in active mode (i.e., the behavior of operating integrated circuits powered by voltage). The criterion for passing the test is the undisturbed operation of the integrated circuit.

Environmental influences or the test itself can cause voltages and currents significantly higher than the maximum specified values for integrated circuits. Immunity analysis at the IC level has the advantage of not requiring consideration of the influence of the device’s design on EMC. This includes, for example, the layout of the printed circuit board, the type and availability of connectors, or the design of the enclosure. Moreover, when testing the immunity of an integrated circuit, the effects of disturbances are less pronounced than during testing of the entire device—this results in better test repeatability. This article describes the connection between device-level testing and pin-level testing of the integrated circuit.

Device Testing

Due to the continuous increase in digitization and the widespread use of electronic components, many devices require a high level of immunity. It is particularly important to carry out immunity tests against impulse disturbances when testing technical objects and devices. This results from the fact that they will be exposed to impulse disturbances during both operation and normal use.

Appropriate disturbance impulses (burst and ESD) in immunity tests are described in the following standards: IEC 61000-4-4 “Fast transient immunity test (burst)” and IEC 61000-4-2 “Electrostatic discharge (ESD) immunity test”:

Figure 1. Burst pulse time curve (fast transient immunity test) compliant with IEC 61000-4-4

Figure 2. ESD pulse time curve (electrostatic discharge immunity test) compliant with IEC 61000-4-2


For a source impedance of 50 Ω, pulses with a minimum voltage of ±2 kV are applied to the device, with a rise time of 5 ns and a fall time of 50 ns (half amplitude – see Figure 1). These pulses constitute the BURST impulses. For a source impedance of 330 Ω, pulses of at least ±6 kV are applied to the device, with a rise time of 0.7 ns and a fall time of 5 ns (half amplitude – Figure 2).

Basic Principles of Device Testing for Interference

To test immunity, a disturbance in the form of an impulse is applied to the device, both in its intended location and independently of it. The primary disturbance impulse (ESD or burst) of voltage u(t) applied to the device causes a flow of disturbance current i(t) through
the device (Figure 3). Two primary mechanisms—magnetic coupling and electric field coupling (E-field)—although they occur simultaneously, should be considered separately.

1. Magnetic Field Coupling H (Inductive)

Magnetic field interference H(t) is formed around a conductor carrying interference current i(t). The lower the impedance of the primary circuit, the greater the current flow and, therefore, the stronger the magnetic field H.

In the ideal case, the field intensity around a straight conductor is determined by equation (1):



Magnetic field disturbances penetrate through the device and the surrounding components as well as the printed circuit boards. Conductor loops are located on the PCBs or within components (e.g., integrated circuits, Figure 3). Magnetic field disturbances generate a secondary disturbance voltage u_sec(t) on inductance L – see equation (2):



This disturbance voltage potentially occurs, for example, in internal circuits of the IC, which may cause malfunction of the component.

2. Electric Field Coupling

The primary disturbance impulse (ESD or burst) of voltage u(t) applied to the device causes a voltage drop across the assembly (Figure 4). The electric field E(t) is generated from the voltage difference along the observed geometry. The higher the impedance of the primary current path, the greater the voltage difference, and thus the higher the resulting E-field. The E-field carries disturbances as displacement current i(t) in secondary loops such as signal cables and/or IC pins through capacitive coupling. The process occurs via the coupling capacitance C, which is in the fF range – see equation (3). The interference voltage is produced across the internal resistance of the secondary loop by the capacitively coupled current i(t). This disturbance voltage may appear at an integrated circuit pin and trigger malfunctions in its operation.



In both cases (coupling caused by the magnetic or electric field), the disturbance is attenuated by a factor of one (device coefficient) during the transition from the primary disturbance circuit to the secondary loop and is localized on the active electronic circuit (e.g., an IC). The interference voltages of 6 kV typically present during an ESD test are reduced to values ranging from 0.1 V to several hundred volts. This reduction depends on the impedance in the primary and secondary disturbance circuits.

ICs mounted on a printed circuit board are exposed to both magnetic H(t) and electric E(t) fields.

Figure 3. Magnetic field coupling mechanisms in an electrical device

Figure 4. E-field coupling mechanisms in an electrical device

Figure 5. Model of coupling with an IC through a magnetic field

Magneto-field (Inductive) Coupling in Integrated Circuits

The magnetic flux density Bst(t) penetrates the smallest conductor loops (e.g., between the IC and the decoupling capacitor – Figure 5). The voltage Ust is induced in the loop of the circuit by the magnetic flux Φ, as described in equations (4) and (5):



The voltage Ust drives interference current into the IC. The impedance of this interference source is low due to the formation of the signal in the conductor loop. This may lead to the generation of high-magnitude interference currents Ist(t).

Electric Field Coupling E (Capacitive) in Integrated Circuits

The electric field intensity E(t), or the displacement current D(t) associated with the conductive surface, generates disturbances Ist(t) in the conductor (Figure 6). These disturbances cause an increase in the voltage Ust(t) on the conductive surface, which may distort the logical signals transmitted through tracks. The displacement current Ist(t) can also propagate to ICs and trigger further disturbances. The source of the “electric field” disturbance has high impedance.

Figure 6. Model of coupling with an IC through an electric field

Figure 7. Example of estimating interference voltage at the IC pin during electric field coupling

Simulation

The following simulations (Figures 7...11) are based on certain simplifications. In Figure 7, the generation of the ESD impulse is significantly simplified. The equivalent circuit is based on the principles of capacitive coupling shown in Figure 4.

Estimating Interference Voltage on the Integrated Circuit

A positive interference pulse with an amplitude of 6 kV is injected as a contact discharge into the primary disturbance circuit (Figure 7). A peak interference voltage (Ust) of 1.4 kV is generated on the primary impedance R1 (Figure 8). An interference voltage of 13.5 V remains in contact with the pin of the integrated circuit with high impedance through capacitive coupling (E-field coupling) via C1. The primary disturbance circuit impedance may be significantly higher (1 kΩ), causing the interference voltage at the IC pin to exceed 100 V, which risks a significant overvoltage beyond the IC’s rated specifications.

Coupling Modes

The type of coupling also depends on the ratio between the source impedance and the load impedance, i.e., the input impedance of the integrated circuit.

Figure 8. Curve and peak values of the interference voltage coupled in the primary and secondary circuits

Figure 9. Equivalent circuit of differential effects of interference coupling through the electric field

Electric Field Coupling E (Capacitive)

With a 1 ns rise time corresponding to a maximum transfer speed of 1 GHz, the coupling capacitance C1 is assumed to be 1 pF. The impedance X of this capacitance is then 159 Ω. If the input resistance of the IC is 10 kΩ, it is significantly higher than the source resistance (C1 impedance).
Thus, the adjacent interference impulse on R2 (on the IC) has the same waveform as the primary interference impulse. This results in a proportional voltage division using the capacitive divider C1, C2.



Completely different conditions occur when the load impedance is lower than the source impedance. The following example assumes R2 = 100 Ω, C1 = 10 fF.



Under these conditions, the main interference impulse is distinguishable in the integrated circuit (Figures 9 and 10).

Magnetic Field Coupling H

In the case of magnetic field coupling, the conditions are reversed. In the resting state:

Ric » Xss = differential behavior,

Ric ‹ Xss = current division.

The summary of coupling mechanisms is shown in Figure 11. In the case of magnetic field coupling, a transformer equivalent circuit is assumed, with the main inductance (Lh) and leakage inductance (Ls).



Figure 10. Differential curve of interference coupling effects through the electric field

Figure 11. Operating zones of coupling mechanisms in integrated circuits: current and voltage division/differentiation