Testing integrated circuits

The main advantage of analyzing the immunity of a device at the integrated circuit (IC) level is that such an examination does not require taking into account the influence of the construction of the said device on electromagnetic compatibility (EMC). This analysis includes, for example, the design of the printed circuit board (PCB), the nature and availability of the connector, and the housing. The article describes the relationship between tests at the device level and at the integrated circuit (IC) level.

Introduction

Ensuring compliance with EMC standards is becoming an increasingly demanding issue. Technological progress has enabled the reduction in component size, but it has also created a specific challenge—controlling the device's immunity to electromagnetic interference.

Current immunity requirements significantly increase the costs of device design and production. However, testing immunity at the component level (i.e., integrated circuits) makes it easier to identify and take corrective actions. The results of immunity tests allow for a preliminary selection of specific integrated circuits (including ASICs) for further product development. Additionally, they can be included in the analysis of integrated circuits and contribute to the optimization of components.

Although there are already test procedures in the industry that have enabled the accumulation of extensive experience in evaluating the immunity of integrated circuits, the concept behind the current testing method introduces a certain change. It involves applying disturbance pulses directly to the pins of the tested integrated circuits. The shape and amplitude of the applied disturbances are specifically selected to simulate typical phenomena that an integrated circuit would be exposed to during a standard device immunity test or while operating in a disturbed environment.

During operation, technical equipment, objects, and devices are usually powered by pulsed interfering signals. Therefore, standard device tests simulate, for example, spark generation at a switch contact (burst) or electrostatic discharge (ESD).

In the case of the standard testing method, immunity is observed in the active mode (i.e., the behavior of operating integrated circuits powered by voltage). The test pass criterion is the undisturbed functioning of the integrated circuit.

Environmental influences or the test itself may cause voltages and currents significantly exceeding the maximum specified values for integrated circuits. Immunity analysis at the integrated circuit level has the advantage of not requiring the influence of device construction on EMC to be considered. This includes, for example, PCB design, connector type and availability, or housing design. Moreover, during IC-level immunity testing, the effects of disturbances are less pronounced than during whole device testing—resulting in better repeatability of test results. This article describes the link between device testing and pin-level testing of integrated circuits.

Device Testing

Due to the continuous growth of digitization and the widespread use of electronic components, many devices require a high level of immunity. It is particularly important to perform impulse disturbance immunity tests when examining technical objects and devices. This is due to the fact that they will be exposed to impulse disturbances during operation and standard use.

Figure 1. Time curve of the burst impulse (fast transient immunity test) according to IEC 61000-4-4

Figure 2. Time curve of the ESD impulse (electrostatic discharge immunity test) according to IEC 61000-4-2

The appropriate interference pulses (burst and ESD) in immunity tests are described in the following standards: IEC 61000-4-4 “Electrical fast transient/burst immunity test” and IEC 61000-4-2 “Electrostatic discharge (ESD) immunity test”:

With a source impedance of 50 Ω, pulses with a minimum voltage of ±2 kV are applied to the device, with a rise time of 5 ns and a fall time of 50 ns (half amplitude – see Figure 1). These pulses form the BURST impulses. With a source impedance of 330 Ω, pulses of at least ±6 kV are applied to the device with a rise time of 0.7 ns and a fall time of 5 ns (half amplitude – Figure 2).

Basic Principles of Device Disturbance Testing

To test immunity, a disturbance in the shape of a pulse is applied to the device, both at its intended location and independently of it. The primary disturbance pulse (ESD or burst) voltage u(t) applied to the device causes the flow of a pulsed interference current i(t) through the device (Figure 3). Two basic mechanisms—magnetic coupling and electric field (E-field) coupling—although occurring simultaneously, should be considered individually.

1. Magnetic Field Coupling H (Inductive)

The magnetic field H(t) interference forms around the conductor carrying the interference current i(t). The lower the impedance of the primary circuit, the higher the current flow, and thus the stronger the magnetic field H.

Ideally, the field strength around a straight conductor is determined by formula (1):



Magnetic field disturbances penetrate through the device and surrounding components, as well as through printed circuit boards. Conductor loops are located on PCBs or in components (e.g., IC, Figure 3). Magnetic field disturbances generate a secondary interference voltage u_sec(t) across inductance L – see formula (2):



This interference voltage may potentially occur, for example, in the internal circuits of the integrated circuit, which can cause malfunctions in the operation of this component.

2. Electric Field Coupling

The basic disturbance impulse (ESD or burst) of the voltage u(t) applied to the device causes a voltage drop across the assembly (Figure 4). The electric field E(t) is obtained from the voltage difference along the observed geometry. The higher the impedance of the primary current path, the greater the voltage difference, and thus the higher the resulting E field. The E field transfers disturbances as displacement current i(t) in secondary loops, such as signal cables and/or integrated circuit pins, through capacitive coupling. This process occurs via the coupling capacitance C, which is in the fF range – see formula (3). The interference voltage is generated across the internal resistance of the secondary loop by the capacitively coupled current i(t). This interference voltage can be present at the integrated circuit pin and trigger disturbances in its operation.



In both cases (coupling caused by the magnetic field or the E field), the disturbance is reduced by a factor of one (device factor) during the transition from the primary disturbance circuit to the secondary loop and is located on the active electronic system (e.g., the integrated circuit). Interference voltages of 6 kV, which typically occur during ESD device testing, are reduced to values ranging from 0.1 V to several hundred volts. This drop depends on the impedance in the primary and secondary disturbance circuits.

Integrated circuits mounted on a printed circuit board are exposed to magnetic fields H(t) and electric fields E(t).

Figure 3. Magnetic field coupling mechanisms in an electrical device

Figure 4. E field coupling mechanisms in an electrical device

Figure 5. Model of coupling to the integrated circuit through the magnetic field

Magnetic field (inductive) coupling in integrated circuits

The magnetic flux density Bst(t) penetrates the smallest conductor loops (e.g., between the integrated circuit and the connected decoupling capacitor – Figure 5). A voltage Ust is induced in the circuit loop by the magnetic flux Φ, as described in (4) and (5):



The voltage Ust supplies a disturbance current to the integrated circuit. The impedance of this disturbance source is low due to signal formation in the conductor loop. This can lead to the formation of high-intensity currents Ist(t).

Electric field E (capacitive) coupling in integrated circuits

The electric field intensity E(t) or the displacement current D(t) associated with the conductive surface generates disturbances Ist(t) in the conductor (Figure 6). These disturbances cause a voltage rise Ust(t) on the conductive surface, which can distort logic signals transmitted through the tracks. The displacement current Ist(t) can also propagate to integrated circuits and trigger further disturbances. The disturbance source of the "electric field" type has high impedance.

Figure 6. Model of coupling to the integrated circuit through the E field

Figure 7. Example of estimating the interference voltage at the integrated circuit pin during coupling of electric interference fields

Simulation

The following simulations (Figures 7...11) are based on certain simplifications. In Figure 7, the generation of the ESD pulse has been significantly simplified. The equivalent circuit is based on the principles of capacitive coupling, shown in Figure 4.

Estimation of interference voltage on the integrated circuit

A positive interference pulse with an amplitude of 6 kV is injected as a contact discharge into the primary disturbance circuit (Figure 7). A peak interference voltage (Ust) of 1.4 kV is generated on the primary impedance R1 (Figure 8). An interference voltage of 13.5 V remains in contact with the high-impedance pin of the integrated circuit through capacitive coupling (E-field coupling) via C1. The impedance of the primary disturbance circuit can be significantly higher (1 kΩ), causing the interference voltage at the integrated circuit pin to exceed 100 V, which poses a serious risk of exceeding the maximum rated values of the integrated circuits.

Coupling modes

The type of coupling also depends on the ratio of the source impedance to the load impedance, i.e., the input impedance of the integrated circuit.

Figure 8. Curve and peak values of coupled interference voltage in the primary and secondary circuits

Figure 9. Equivalent circuit of differentiating effects of interference coupling through the electric field

Electric field E (capacitive) coupling

With a 1 ns rise time resulting in a maximum transfer rate of 1 GHz, it is assumed that the coupling capacitance C1 equals 1 pF. The impedance X of this capacitance then assumes a value of 159 Ω. When the input resistance of the integrated circuit is 10 kΩ, it is much greater than the source resistance (the impedance of C1).
As a result, the adjacent interference pulse on R2 (on the integrated circuit) has the same waveform as the original interference pulse. This causes a proportional voltage division via the capacitive divider C1, C2.



Completely different conditions arise when the load impedance is lower than the source impedance. The following example assumes R2 = 100 Ω, C1 = 10 fF.



Under these conditions, the main interference pulse is distinguished in the integrated circuit (Figures 9 and 10).

Magnetic field H coupling

In the case of coupling with the H field, the conditions are reversed. In the idle state:

Ric » Xss is differentiated,

Ric ‹ Xss is current-divided.

A summary of the coupling mechanisms is shown in Figure 11. For H-field coupling, a transformer equivalent circuit with main inductance (Lh) and leakage inductance (Ls) is assumed.



Figure 10. Curve differentiating interference coupling effects through the electric field

Figure 11. Operating regions of integrated circuit coupling mechanisms: division/differentiation of currents and voltages